1. Technical Field
The present invention relates generally to integrated circuit (IC) design, and more particularly to process aid generation.
2. Related Art
In semiconductor manufacturing, there is a continual pursuit of making chips smaller and producing as many chips as possible from a single wafer. As part of this pursuit, as shown in FIG. 1, chips 2 are placed in a matrix across a wafer 4 as close as possible. The space between chips, referred to as a kerf 6, channel, scribe, or street (hereinafter “kerf”), is also a focus of minimization. Kerfs are necessary to provide room for dissecting of the chips from one another, but also provide room for structures used during processing that do not ultimately constitute part of the chips. These devices are referred to herein as “process aids.” Kerf design minimization is difficult because: (1) the number of process aids that need to be placed therein is immense, and (2) the sharp diversity between process aid types. For example, electrical process aids are used to mimic the IC, providing information to characterize the process. Some optical process aid applications include controlling overlay, field-to-field alignment, line width resolution, as well as providing necessary tooling alignment aids.
In view of the foregoing, kerf design has become an increasingly important stage of semiconductor manufacturing. Conventionally, kerf design was achieved by hand drawing all the process aids and placing them in libraries. All similar optical devices were placed in an optical library, and all electrical devices were placed in an electrical library for the various technologies. To address new technologies, these existing libraries were copied and manually modified to meet the various requirements as laid out in the design manual for the respective technology. As design rule requirements for new technologies have become more rigorous, the data volumes for each of these libraries has increased and become much more complex. As a further consequence, ensuring data integrity so the various structures can be used is very difficult. For example, each process aid must be able to be located on the wafer in order for it to be used, and particular operational data about various aids, e.g., capacitances, resistances, etc., must be available for use by testers. However, conventional manual design of kerfs makes generation of this information extremely difficult, and very time consuming for the kerf designer.
In view of the foregoing, there is a need in the art for a way to automate process aid generation to address the problems of the related art.